The invention relates generally to semiconductor devices and in particular to semiconductor transistor devices having reduced channel widths and methods of fabricating same.
As will be appreciated, transistors, such as MOSFETs (metal oxide field effect transistors), generally include a number of layers wherein many doped regions are formed. Unlike silicon-based devices, wherein doped regions are typically formed by diffusion, the doped regions in silicon carbide (SiC) based devices are generally formed through ion implantation. Thus, for certain devices, such as SiC-based devices, the formation of the various doped regions is achieved through ion implantation which may be conducted through one or more openings formed through a series of lithography steps.
For instance, for a power MOSFET device, the channel formation typically involves the deposition and patterning of at least two photolithographic layers. Specifically, in conventional techniques, a P-type well is formed in an N-epitaxial drift region by employing a first photolithographic process. As will be appreciated, this photolithographic process generally involves disposing a masking layer, such as a photoresist, and patterning the layer to expose a portion of the underlying N-epitaxial drift region. The P-type well may then be formed through the opening by ion implantation, using a p-type dopant, such as boron or aluminum. As will be appreciated, the structure of a power MOSFET provides for an N+ doped source region to be surrounded by the P-type well region to form a channel for the MOSFET. The N+ doped source region is generally formed by employing a second photolithographic process, employing another masking layer which is disposed and patterned to provide an opening such that the N+ doped source region can be formed through ion implantation, for instance.
Disadvantageously, relying on the alignment of multiple lithography steps to form the channel of a power MOSFET limits the manufacturability of the channel. Specifically, channel dimensions are generally set on the order of 1 micron or greater to account for any misalignments caused by employing multiple lithography processes. Accordingly, channel widths formed using conventional lithography steps and multiple masking layers generally result in devices designed to have channel widths sufficiently greater than 1 micron, in order to fall within conventional tolerance limits. Disadvantageously, larger channel dimensions cause a higher on-state resistance of the device, as well as higher power dissipation.
Therefore there is a need to reduce the number of steps involved in fabrication and to reduce the channel dimension of power MOSFET devices. Accordingly, a technique is needed to address one or more of the foregoing problems in the fabrication of semiconductor devices.